Analog-to-digital converters are utilized in applications where it is required to convert an analog signal into a digital form for processing by a digital system. A schematic diagram of a prior art ten-bit successive-approximation analog-to-digital converter (ADC) is shown in FIGS. 1A and 1B. The ADC includes three main elements: a control logic circuit 101, a digital-to-analog converter (DAC) 103, and an analog comparator 105. DAC 103 includes a resistor string comprised of resistors R101 through R116 for converting a four-bit binary value to an analog value and a weighted-capacitor array comprising capacitors C101 through C107 for converting a six-bit binary value to an analog value. Switches S101 through S125 are controlled such that any ten-bit binary value can be converted into an analog value, the four most significant bits of the ten-bit binary value being converted by the resistor string and the remaining six bits being converted by the capacitor array.
The converter operation is as follows. With switch S118 open, switch S126 closed, switches S120 through S125 placed in position "2" and switch S119 placed in position "3" the bottom plates of capacitors C101 through C107 are connected to sample and hold the unknown analog voltage (VIN) to be converted. After opening switch S126, a successive-approximation search among the resistor string taps is conducted to find the voltage segment within which the stored unknown analog voltage lies. During this search the converter successively divides in half the voltage range in which the comparator has placed the unknown analog voltage. Then, with switches S101 through S119 set to connect the ends of the resistor which defines this segment to buses 118 and 119, the capacitor bottom plates are switched in a successive-approximation sequence until the voltage potential of the top plate of the capacitor array, i.e., the voltage level provided to comparator 105, is equal to ground potential.
The following example is provided to aid in the understanding of the operation of the converter. Assume that the VREF equals 16 volts and the unknown analog voltage VIN equals 7.8 volts. With VREF equal to 16 volts the voltage drop across each resistor R101 through R116 is 1 volt. Prior to initiation of the successive approximation search, capacitors C101 through C107 are charged to -7.8 volts (top plates relative to bottom plates) following the procedure set forth in the preceding paragraph.
The steps in the successive approximation search are as follows, each step taking one clock cycle. The search begins with switches S120 through S125 placed in their "3" positions, switch S108 closed and switch S119 set to position 2. Thus the voltage potential of the bottom plates of the capacitor array is set to 8 volts (the analog equivalent to binary value 1000000000), and the voltage potential of the top plates, which is provided to the minus input of comparator 105, is 0.2 volts. The comparator output indicates that VIN is less than 8 volts so during the next search step switch S108 is opened and switch S104 is closed providing a voltage potential of 4 volts to the capacitor bottom plates. The top plate voltage is now -3.8 volts. The comparator output indicates that VIN is greater than 4 volts. During the third search step switch S104 is open and switch S106 is closed providing 6 volts to the bottom plates of the capacitor array and -1.8 volts to the top plates. The fourth search step provides 7 volts to the bottom plates of the capacitors by closing switch S107 and setting switch S119 to position "1". The top plate voltage will be -0.8 volts. Thus, after four clock cycles it is determined that the unknown analog voltage VIN lies between 7 and 8 volts.
At the onset of the search among capacitors C101 through C107, switches S107 and S108 are closed, switches S118 and S119 are positioned to provide 7 volts to bus 119 and 8 volts to bus 118, switches S120 through S124 are set to their "2" positions and switch A125 is set to position "1". After redistribution of the charge among the capacitors, the potential of the top plate of the capacitors will be -0.3 volts. For the sixth search step switches S125 and S124 are set to their "1" position. The potential of the top plate of the capacitor array will equalize at -0.05 volts. A total of ten search steps will be conducted as shown in the table provided below. The voltages shown in steps 7 through 10 have been rounded off at the hundredths decimal place. At the conclusion of the search the binary equivalent of VIN will be determined to be 0111110011, the last value to produce a "yes" answer to the comparison.
TABLE 1 ______________________________________ Step Comparison Answer Binary Value ______________________________________ 1 8.00 V-VIN &lt;= OV No 1000000000 2 4.00 V-VIN &lt;= OV Yes 0100000000 3 6.00 V-VIN &lt;= OV Yes 0110000000 4 7.00 V-VIN &lt;= OV Yes 0111000000 5 7.50 V-VIN &lt;= OV Yes 0111100000 6 7.75 V-VIN &lt;= OV Yes 0111110000 7 7.88 V-VIN &lt;= OV No 0111111000 8 7.81 V-VIN &lt;= OV No 0111100100 9 7.78 V-VIN &lt;= OV Yes 0111100010 10 7.80 V-VIN &lt;= OV Yes 0111110011 ______________________________________
During the sample period the capacitor array is charged to -VIN (top plate voltage relative to bottom plate). The control logic begins the successive approximation sequence by setting the bottom plates of capacitors C101 through C107 at a voltage equal to VREF/2, the voltage at the midpoint of the resistor string. The voltage potential of the top plate of the capacitor array will therefore equal (VREF/2) -VIN during the onset of the successive approximation sequence. If the potential of VIN is between zero and VREF then the voltage swing on the top plate of the capacitor array is -VREF/2 to VREF/2. Thus, the voltage on the top plate of the capacitor array will be outside of voltage range defined by the supply rails for VREF between 0 and VDD causing parasitic diodes to turn on which will remove charge from the capacitor array.
A difficulty associated with prior art analog-to-digital converter architectures is that they generally have restricted references and/or input voltage ranges, frequently equal to one half of the supply span. To achieve higher voltage ranges, converter accuracy must be sacrificed.
The following articles, incorporated herein by reference, provide details on the construction and digital converters and components thereof. digital converts and components thereof.
(1) "All MOS Charge Redistribution Analog-to-Digital Conversion Techniques--Part I"by James McCreary and Paul Gray, IEEE Journal of Solid State Circuits, Volume SC-10, pp 371-379, December 1975.
(2) "High Resolution A/D Conversion in MOS/LSI" by Bahram Fotouhi and David A. Hodges, IEEE Journal of Solid State Circuits, Volume SC-11, (Number 6, December 1976.
(3) "A 10-bit 5-Msample/s CMOS Two-Step Flash ADC" by Joey Doernberg, Paul R. Gray and David A. Hodges, IEEE Journal of Solid State Circuits, Volume 24, Number 2, April 1989.